PIC24F04KA201 datasheet(3/26 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39991A-page 3

PIC24FXXKA2XX

2.2

Memory Map

The program memory map extends from 000000h to

FFFFFEh. Code storage is located at the base of the

memory map, and supports up to about 1.38 K words

of instructions (about 4 Kbytes). Figure 2-2 depicts the

memory map.

Table 2-2 provides the program memory size and

number of program memory rows present in each

device variant.

The erase operation can be done on one word, half of

a row or one row at a time. The program operation can

be done only one word at a time.

The device Configuration registers are implemented

from location, F80000h to F80010h, and can be erased

or programmed one register at a time. Table 2-3 pro-

vides the implemented Configuration registers and

their locations.

Locations, FF0000h and FF0002h, are reserved for the

Device ID registers. These bits can be used by the

programmer to identify the device type that is being

programmed. See Section 4.0 “Device ID” for more

information. The Device ID registers read out normally

even after code protection is applied.

TABLE 2-2:

PROGRAM MEMORY SIZES

TABLE 2-3:

CONFIGURATION REGISTER

LOCATIONS

FIGURE 2-2:

PROGRAM MEMORY MAP

Device

Program Memory

Upper Address

(Instruction Words)

Rows

PIC24F04KA200

AFEh (1.375K)

PIC24F04KA201

Configuration Register

Address

FGS

F80004

FOSCSEL

F80006

FOSC

F80008

FWDT

F8000A

FPOR

F8000C

FICD

F8000E

FDS

F80010

000000h

Code Memory

(2816 x 24-bit)

800000h

Device ID

FEFFFEh

FF0000h

FFFFFEh

Reserved

8007F0h

FF0002h

FF0004h

Reserved

(2 x 16-bit)

User Flash

8007EEh

Configuration Registers

F80010h

F80000h

Diagnostic Words

800800h

8007FEh

000AFEh

Reserved

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