EM773 datasheet(33/45 Pages) NXP

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EM773

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Objective data sheet

Rev. 1 — 1 September 2010

33 of 45

NXP Semiconductors

EM773

Energy metering IC

[6]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8]

The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9]

tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT =

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period

of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus

specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

10.6 SPI interfaces

Fig 18. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

Table 12.

Dynamic characteristics of SPI pins in SPI mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SPI master (in SPI mode)

Tcy(clk)

clock cycle time

when only receiving

[1]

when only transmitting [1]

27.8

tDS

data set-up time

in SPI mode

2.4 V

≤ V

DD ≤ 3.6 V

[2]

2.0 V

≤ V

DD < 2.4 V

[2]

1.8 V

≤ V

DD < 2.0 V

[2]

tDH

data hold time

in SPI mode

[2]

tv(Q)

data output valid time in SPI mode

[2]

th(Q)

data output hold time in SPI mode

[2]

SPI slave (in SPI mode)

Tcy(PCLK)

PCLK cycle time

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