TMS320F2812 datasheet(39/170 Pages) TI

39 / 170 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S – APRIL 2001 – REVISED MARCH 2011

3.3

The F281x and C281x devices contain three peripheral register spaces. The spaces are categorized as

follows:

Peripheral Frame 0:

These are peripherals that are mapped directly to the CPU memory bus.

See Table 3-6.

Peripheral Frame 1:

These are peripherals that are mapped to the 32-bit peripheral bus.

See Table 3-7.

Peripheral Frame 2:

These are peripherals that are mapped to the 16-bit peripheral bus.

See Table 3-8.

Table 3-6. Peripheral Frame 0 Registers(1)

NAME

ADDRESS RANGE

SIZE (x16)

ACCESS TYPE(2)

Device Emulation Registers

0x00 0880 – 0x00 09FF

384

EALLOW protected

Reserved

0x00 0A00 – 0x00 0A7F

128

EALLOW protected

FLASH Registers(3)

0x00 0A80 – 0x00 0ADF

CSM Protected

Code Security Module Registers

0x00 0AE0 – 0x00 0AEF

EALLOW protected

Reserved

0x00 0AF0 – 0x00 0B1F

XINTF Registers

0x00 0B20 – 0x00 0B3F

Not EALLOW protected

Reserved

0x00 0B40 – 0x00 0BFF

192

CPU-TIMER0/1/2 Registers

0x00 0C00 – 0x00 0C3F

Not EALLOW protected

Reserved

0x00 0C40 – 0x00 0CDF

160

PIE Registers

0x00 0CE0 – 0x00 0CFF

Not EALLOW protected

PIE Vector Table

0x00 0D00 – 0x00 0DFF

256

EALLOW protected

Reserved

0x00 0E00 – 0x00 0FFF

512

(1)

Registers in Frame 0 support 16-bit and 32-bit accesses.

(2)

If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS

instruction disables writes. This prevents stray code or pointers from corrupting register contents.

(3)

The Flash Registers are also protected by the Code Security Module (CSM).

Table 3-7. Peripheral Frame 1 Registers(1)

NAME

ADDRESS RANGE

SIZE (x16)

ACCESS TYPE

256

Some eCAN control registers (and selected bits in

eCAN Registers

0x00 6000 – 0x00 60FF

(128 x 32)

other eCAN control registers) are EALLOW-protected.

256

eCAN Mailbox RAM

0x00 6100 – 0x00 61FF

Not EALLOW-protected

(128 x 32)

Reserved

0x00 6200 – 0x00 6FFF

3584

(1)

The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.

Functional Overview

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