TMS320F2812 datasheet(124/170 Pages) TI

전자부품 데이터시트 검색엔진

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TMS320F2812 데이터시트(PDF) 124 Page - Texas Instruments

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SPISIMO

SPISOMI

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

SPISIMO Data

Must Be Valid

Data Valid

SPISOMI Data Is Valid

SPISTE

(A)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S – APRIL 2001 – REVISED MARCH 2011

www.ti.com

In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and

remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

Figure 6-29. SPI Slave Mode External Timing (Clock Phase = 1)

124

Electrical Specifications

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

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