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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMS320F2812 데이터시트(PDF) 131 Page - Texas Instruments |
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TMS320F2812 데이터시트(HTML) 131 Page - Texas Instruments |
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131 / 170 page  DIN t d(XCOHL-XRDL) t d(XCOH-XA) t d(XCOH-XZCSL) t d(XCOHL-XRDH) t h(XD)XRD t d(XCOHL-XZCSH) XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XZCS0AND1 XZCS2 XZCS6AND7 , , XA[0:18] XRD XWE XR/W XD[0:15] t su(XD)XRD t a(A) t a(XRD) XREADY Lead Active Trail TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 www.ti.com SPRS174S – APRIL 2001 – REVISED MARCH 2011 A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals will transition to their inactive state. C. For USEREADY = 0, the external XREADY input signal is ignored. D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles. Figure 6-31. Example Read Access XTIMING register parameters used for this example: XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE ≥ 1 ≥ 0 ≥ 0 0 0 N/A(1) N/A(1) N/A(1) N/A(1) (1) N/A = “Don’t care” for this example Copyright © 2001–2011, Texas Instruments Incorporated Electrical Specifications 131 Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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