TMP320LC2401AVFS datasheet(76/88 Pages) TI

76 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

internal ADC module timing† (see Figure 39)

MIN

MAX

UNIT

tc(AD)

Cycle time, ADC prescaled clock

33.3

tw(SHC)

Pulse duration, total sample/hold and conversion time‡

500

tw(SH)

Pulse duration, sample and hold time

2tc(AD)§

32tc(AD)

tw(C)

Pulse duration, total conversion time

10tc(AD)

td(SOC-SH)

Delay time, start of conversion to beginning of sample and hold

2tc(CO)

td(EOC)

Delay time, end of conversion to data loaded into result register

2tc(CO)

td(ADCINT)

Delay time, ADC flag to ADC interrupt

2tc(CO)

† The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the TMS320LF/LC240xA DSP Controllers

Reference Guide: System and Peripherals (literature number SPRU357) for more details.

‡ The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC).

§ Can be varied by ACQ Prescaler bits in the ADCCTRL1 register

tw(C)

tc(AD)

ADC Clock

Analog Input

Bit Converted

td(SOC−SH)

EOC/Convert

Internal Start/

Sample Hold

Start of Convert

XFR to RESULTn

tw(SHC)

td(EOC)

tw(SH)

td(ADCINT)

ADC Interrupt

Figure 39. Analog-to-Digital Internal Module Timing

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