SC1205

HIGH SPEED SYNCHRONOUS POWER

MOSFET DRIVER

© 1999 SEMTECH CORP.

652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - December 7, 1999

10

can often eliminate the EMI issue. If double pulsing is

caused due to excessive ringing, placing 4.7-10 ohm

resistor between the phase node and the DRN pin of

the SC1205 should eliminate the double pulsing.

Proper layout will guarantee minimum ringing and

eliminate the need for external components. Use of

SO-8 or other surface mount MOSFETs while increas-

ing thermal resistance, will reduce lead inductance as

well as radiated EMI.

OVER TEMP SHUTDOWN

The SC1205 will shutdown by pulling both driver if its

junction temperature, Tj, exceeds 165 °C.

While not shown in Figure 3, a capacitor may be

added from the gate of the Bottom FET to its source,

preferably less than .1” away. This capacitor will be

added to Ciss in the above equation to reduce the ef-

fective spike voltage, Vspike.

The selection of the bottom MOSFET must be done

with attention paid to the Crss/Ciss ratio. A low ratio

reduces the Miller feedback and thus reduces Vspike.

Also MOSFETs with higher Turn-on threshold voltages

will conduct at a higher voltage and will not turn on

during the spike. The MOSFET shown in the

schematic (figure 3) has a 2 volt threshold and will re-

quire approximately 4.5 volts Vgs to be conducting,

thus reducing the possibility of shoot-through. A zero

ohm bottom FET gate resistor will obviously help

keeping the gate voltage low.

Ultimately, slowing down the top FET by adding gate

resistance will reduce di/dt which will in turn make the

effective impedance of the capacitors higher, thus al-

lowing the BG driver to hold the bottom gate voltage

low. It does this at the expense of increased switching

times ( and switching losses) for the top FET.

RINGING ON THE PHASE NODE

The top MOSFET source must be close to the bottom

MOSFET drain to prevent ringing and the possibility of

the phase node going negative.

This frequency is

determined by:

F

Where:

L

added to trace inductance of the connection between

top FET’s source and the bottom FET’s drain added to

the trace resistance of the bottom FET’s ground con-

nection.

Coss=Drain to source capacitance of bottom FET. If

there is a Shottkey used, the capacitance of the Shot-

tkey is added to the value.

Although this ringing does not pose any power losses

due to a fairly high Q, it could cause the phase node

to go too far negative, thus causing improper opera-

tion, double pulsing or at worst driver damage. On the

SC1205, the drain node, DRN, can go as far as 2V

below ground without affecting operation or sustaining

damage.

The ringing is also an EMI nuisance due to its high

resonant frequency. Adding a capacitor, typically

1000-2000pf, in parallel with Coss of the bottom FET