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ESDA25LY 데이터시트(PDF) 4 Page - STMicroelectronics

부품명 ESDA25LY
상세설명  Automotive dual Transil array for ESD protection
PDF  10 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ESDA25LY 데이터시트(HTML) 4 Page - STMicroelectronics

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Calculation of the clamping voltage
ESDA25LY
4/10
Doc ID 16914 Rev 1
2
Calculation of the clamping voltage
2.1
Use of the dynamic resistance
The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB
designers need to calculate easily the clamping voltage VCL. This is why we give the
dynamic resistance in addition to the classical parameters. The voltage across the
protection cell can be calculated with the following formula:
VCL = VBR + Rd IPP
Where Ipp is the peak current through the ESDA cell.
3
Dynamic resistance measurement
The short duration of the ESD has led us to prefer a more adapted test wave, as below
defined, to the classical 8/20 µs and 10/1000 µs surges.
As the value of the dynamic resistance remains stable for a surge duration lower than 20 µs,
the 2.5 µs rectangular surge is well adapted. In addition both rise and fall times are
optimized to avoid any parasitic phenomenon during the measurement of Rd.
Figure 9.
2.5 µs duration measurement wave
2µs
t = 2.5µs
p
t
I
IPP



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