DS5000FP datasheet(6/22 Pages) DALLAS

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DS5000FP

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INSTRUCTION SET

The DS5000FP executes an instruction set that is object code compatible with the industry standard 8051

microcontroller. As a result, software development packages such as assemblers and compilers that have

been written for the 8051 are compatible with the DS5000FP. A complete description of the instruction

set and operation are provided in the Secure Microcontroller User’s Guide.

Also note that the DS5000FP is embodied in the DS5000(T) and DS2250(T) modules. The DS5000(T)

combines the DS5000FP with one SRAM of either 8 or 32 kbytes and a lithium cell. An optional Real

Time Clock is also available in the DS5000T. This is packaged in a 40-pin DIP module. The DS2250(T)

is an identical function in a SIMM form factor. It also offers the option of a second 32k SRAM mapped

as data on Chip Enable 2.

MEMORY ORGANIZATION

Figure 2 illustrates the memory map accessed by the DS5000FP. The entire 64k of program and 64k of

data is available. The DS5000FP maps 32k of this space into the SRAM connected to the byte-wide bus.

This is the area from 0000h to 7FFFh (32k) and is reached via CE1 . Any area not mapped into the NV

RAM is reached via the Expanded bus on Ports 0 & 2. Selecting CE2 provides another 32k of potential

data storage. When CE2 is used, no data is available on the ports. The memory map is covered in detail in

the Secure Microcontroller User’s Guide.

Figure 3 illustrates a typical memory connection for a system using 8k bytes of SRAM. Figure 4 shows a

similar system with 32 kbytes. The byte-wide Address bus connects to the SRAM address lines. The bi-

directional byte-wide data bus connects the data I/O lines of the SRAM. CE1 provides the chip enable

and R/ W is the write enable. An additional RAM could be connected to CE2 , with common connections

for R/ W , BA14-0, and BD7-0.

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