7

Integrated

Circuit

Systems, Inc.

ICS9LPRS480

1391D—02/02/09

General Description

Block Diagram

The ICS9LPRS480 is a main clock synthesizer chip that provides all clocks required for ATI RS7xx-based

systems.using AMD processors. An SMBus interface allows full control of the device.

Power Groups

VDD

VDDIO

GND

63

1

USB_48 outputs

47

SRC/27MHz Outputs

16

10,18

SRC Logic Core

11,17

SRC differential outputs (IO's)

35

33

SB_SRC Core Logic

34

SB_SRC differential outputs (IO's)

40

43

SRC/SATA differential output

26

24

ATIG Core Logic

25

ATIG differential outputs (IO's)

48

43

CPUKG Core Logic

47

CPUKG differential outputs (IO's)

55

52

HTTCLK output

56

60

REF outputs

Description

Pin Number

REF(2:0)

CPUKG

OSC

14.318MHz

SB_SRC(1:0)

SRC(5:0)

100MHz

48MHz_(1:0)

X1

X2

Fixed PLL

SS SB_SRC

200MHz

PD#

SEL_SATA

SMBCLK

SMBDAT

Control

Logic

HTT0/66MHz

100MHz

SRC6/SATA

100MHz DIF/66MHz

SS PLL

CPU/HTT, SRC,

ATIG

CLKREQ(5:0)#

100MHz

ATIG(2:0)

SEL_HTT66

SEL_27

27MHz SS PLL

27MHz SS PLL

SRC7C/27MHz_NS

SRC7T/27MHz_SS