FM24C64C

Rev. 1.1

June 2011

2 of 12

Address

Latch

1,024 x 64

FRAM Array

8

SDA

Counter

Serial to Parallel

Converter

Control Logic

SCL

WP

A0-A2

Data Latch

Figure 1. FM24C64C Block Diagram

Pin Description

Pin Name

I/O

Pin Description

A0-A2

Input

Address 2-0: These pins are used to select one of up to 8 devices of the same type on

the same two-wire bus. To select the device, the address value on the three pins must

match the corresponding bits contained in the device address. The address pins are

pulled down internally.

SDA

I/O

Serial Data Address: This is a bi-directional pin used to shift serial data and addresses

for the two-wire interface. It employs an open-drain output and is intended to be wire-

OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt

trigger for noise immunity and the output driver includes slope control for falling

edges. A pull-up resistor is required.

SCL

Input

Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of

the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL

input also incorporates a Schmitt trigger input for improved noise immunity.

WP

Input

Write Protect: When WP is high, addresses in the upper quadrant of the logical

memory map will be write-protected. Write access is permitted to the lower three-

quarters of the address space. When WP is low, all addresses may be written. This pin

is pulled down internally.

VDD

Supply

Supply Voltage: 5V

VSS

Supply

Ground