FM25040B datasheet(8/13 Pages) RAMTRON

8 / 13 page

FM25040B - 4Kb 5V SPI F-RAM

Rev. 1.2

Feb. 2011

Page 8 of

Figure 9. Memory Write

Figure 10. Memory Read

Endurance

Internally, a F-RAM operates with a read and restore

mechanism. Therefore, endurance cycles are applied

for each access: read or write. The F-RAM

architecture is based on an array of rows and

columns. Each access causes a cycle for an entire

row. In the FM25040B, a row is 64 bits wide. Every

8-byte boundary marks the beginning of a new row.

Endurance can be optimized by ensuring frequently

accessed data is located in different rows.

Regardless, F-RAM read and write endurance is

effectively unlimited at the 20MHz clock speed.

Even at 2000 accesses per second to the same row, 15

years time will elapse before 1012 endurance cycles

occur.

34567

op-code

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Byte Address

SCK

LSB

MSB

LSB

Data Out

Hi-Z

LSB

56701

01234567

op-code

MSB

Byte Address

SCK

LSB MSB

LSB

Data

Hi-Z

FM25040B 데이터시트(PDF) 8 Page - Ramtron International Corporation

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