Rev. D 08/11

2

LNK403-409/413-419

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Figure 4.

Pin Configuration.

Pin Functional Description

DRAIN (D) Pin:

This pin is the power FET drain connection. It also provides

internal operating current for both start-up and steady-state

operation.

SOURCE (S) Pin:

This pin is the power FET source connection. It is also the

ground reference for the BYPASS, FEEDBACK, REFERENCE and

VOLTAGE MONITOR pins.

BYPASS (BP) Pin:

This is the connection point for an external bypass capacitor for

the internally generated 5.9 V supply. This pin also provides

output power selection through choice of the BYPASS pin

capacitor value.

FEEDBACK (FB) Pin:

The FEEDBACK pin is used for output voltage feedback. The

current into the FEEDBACK pin is directly proportional to the

output voltage. The FEEDBACK pin also includes circuitry to

protect against open load and overload output conditions.

REFERENCE (R) Pin:

This pin is connected to an external precision resistor and is

used to configure for dimming (LNK403-409) and non-TRIAC

dimming (LNK413-419) modes of operation.

VOLTAGE MONITOR (V) Pin:

This pin interfaces with an external input line peak detector,

consisting of a rectifier, filter capacitor and resistors. The

applied current is used to control stop logic for line under-

voltage (UV), overvoltage (OV), provide feed-forward to control

the output current and the remote ON/OFF function.

PI-5431-102610

DRAIN (D)

SOURCE (S)

BYPASS (BP)

VOLTAGE

MONITOR (V)

FEEDBACK (FB)

REFERENCE (R)

5.9 V

5.0 V

BYPASS PIN

UNDERVOLTAGE

FAULT

PRESENT

Gate

Driver

SenseFet

OCP

CURRENT LIMIT

COMPARATOR

1 V

6.4 V

Comparator

5.9 V

REGULATOR

SOFT-START

TIMER

JITTER

CLOCK

OSCILLATOR

AUTO-RESTART

COUNTER

BYPASS

CAPACITOR

SELECT

FEEDBACK

SENSE

PFC/CC

CONTROL

LINE

SENSE

HYSTERETIC

THERMAL

SHUTDOWN

+

-

+

-

UV/OV

REFERENCE

BLOCK

LEB

STOP

LOGIC

PI-5432-082411

Exposed Pad

(backside) Internally

Connected to

SOURCE Pin (see

eSIP-7C Package

Drawing)

1 R

2 V

3 FB

4 BP

5 S

7 D

E Package (eSIP-7C)

(Top View)

Lead Bend Outward

from Drawing

(Refer to eSIP-7F Package

Outline Drawing)

Exposed Pad

(Backside) Internally

Connected to

SOURCE Pin

7

D

5

S

4

BP

3

FB

2

V

1

R

L Package (eSIP-7F)

Figure 3.

Functional Block Diagram.