HT66F40 datasheet(39/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.60

October 24, 2011

Write Protection

Protection against inadvertent write operation is pro-

vided in several ways. After the device is powered-on

the Write Enable bit in the control register will be cleared

preventing any write operations. Also at power-on the

Bank Pointer, BP, will be reset to zero, which means that

Data Memory Bank 0 will be selected. As the EEPROM

control register is located in Bank 1, this adds a further

measure of protection against spurious write opera-

tions. During normal program operation, ensuring that

the Write Enable bit in the control register is cleared will

safeguard against incorrect write operations.

EEPROM Interrupt

The EEPROM write or read interrupt is generated when

an EEPROM write or read cycle has ended. The

EEPROM interrupt must first be enabled by setting the

DEE bit in the relevant interrupt register. However as the

EEPROM is contained within a Multi-function Interrupt,

the associated multi-function interrupt enable bit must

also be set. When an EEPROM write cycle ends, the

DEF request flag and its associated multi-function inter-

rupt request flag will both be set. If the global, EEPROM

and Multi-function interrupts are enabled and the stack

is not full, a jump to the associated Multi-function Inter-

rupt vector will take place. When the interrupt is serviced

only the Multi-function interrupt flag will be automatically

reset, the EEPROM interrupt flag must be manually re-

set by the application program. More details can be ob-

tained in the Interrupt section.

Programming Considerations

Care must be taken that data is not inadvertently written

to the EEPROM. Protection can be enhanced by ensur-

ing that the Write Enable bit is normally cleared to zero

when not writing. Also the Bank Pointer could be nor-

mally cleared to zero as this would inhibit access to

Bank 1 where the EEPROM control register exist. Al-

though certainly not necessary, consideration might be

given in the application program to the checking of the

validity of new write data by a simple read back process.

· Programming Examples

¨ Reading data from the EEPROM - polling method

MOV

A, EEPROM_ADRES

; user defined address

MOV

EEA, A

MOV

A, 040H

; setup memory pointer MP1

MOV

MP1, A

; MP1 points to EEC register

MOV

A, 01H

; setup Bank Pointer

MOV

BP, A

SET

IAR1.1

; set RDEN bit, enable read operations

SET

IAR1.0

; start Read Cycle - set RD bit

BACK:

IAR1.0

; check for read cycle end

JMP

BACK

CLR

IAR1

; disable EEPROM read/write

CLR

MOV

A, EEDATA

; move read data to register

MOV

READ_DATA, A

¨ Writing Data to the EEPROM

- polling method

MOV

A, EEPROM_ADRES

; user defined address

MOV

EEA, A

MOV

A, EEPROM_DATA

; user defined data

MOV

EED, A

MOV

A, 040H

; setup memory pointer MP1

MOV

MP1, A

; MP1 points to EEC register

MOV

A, 01H

; setup Bank Pointer

MOV

BP, A

SET

IAR1.3

; set WREN bit, enable write operations

SET

IAR1.2

; start Write Cycle - set WR bit

BACK:

IAR1.2

; check for write cycle end

JMP

BACK

CLR

IAR1

; disable EEPROM read/write

CLR

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