HT82V42

Rev. 1.20

13

December 8, 2010

Internal VSMP Pulse Generated by Programmable Internal Sample Detect Circuit

References

The ADC reference voltages are derived from an inter-

nal bandgap reference, and buffered to pins VRT and

VRB, where they must be decoupled to ground. Pin

VRX is driven by a similar buffer, and also requires de-

coupling. The output buffer from the RLCDAC also re-

quires decoupling at pin VRLC/VBIAS.

Power Supply

The HT82V42 can run from a single 3.3V single supply.

Power Management

Power management for the device is performed via the

Control Interface. The device can be powered on or off

completely by clearing the EN bit low.

All the internal registers maintain their previously pro-

grammed value in the power down mode while the Se-

rial Interface inputs remain active.

Line-by-Line Operation

Certain linear sensors (e.g. Contact Image Sensors)

give a colour output on a line-by-line basis. i.e. a full line

of red pixels followed by a line of green pixels followed

by a line of blue pixels.

In this mode the input multiplexer and (optionally) the

PGA/Offset register multiplexers can be auto-cycled by

the application of pulses to the RLC/ACYC input pin by

setting the ACYCNRLC register bit. See Figure for de-

tailed timing information. The multiplexers change on

the first DCLK rising edge after RLC/ACYC is taken

high. A write to the auto-cycle reset register causes

these multiplexers to be reset, selecting the colour R

and the RED offset/gain registers. Alternatively, all three

multiplexers can be controlled via the serial interface by

writing to register bits INTM[1:0] to select the desired

colour. It is also possible for the input multiplexer to be

controlled separately from the PGA and Offset

multiplexers. Table describes all the multiplexer selec-

tion modes that are possible.