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HT82V46 데이터시트(PDF) 13 Page - Holtek Semiconductor Inc

부품명 HT82V46
상세설명  16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
PDF  27 Pages
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제조업체  HOLTEK [Holtek Semiconductor Inc]
홈페이지  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT82V46 데이터시트(HTML) 13 Page - Holtek Semiconductor Inc

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Rev. 1.10
13
November 24, 2011
HT82V46
Reset Level Clamping (RLC)
TherearePixel-ClampingandLine-Clampingtwo
operatingmodesofHT82V46.Itcanbeselectedby
registerbitCLPCTL.Theclampswitchcontrolled
byaninternalCLPsignal,andmustsettheRLCEN
(default=1)registerbitto1toenableclamping.
Pixel-clamping (CLPCTL=0)
• WhenWS=0(NormalMode)andCDS=X(both
forCDSmodeandnon-CDSmode).
TheRLCswitchisclosedwhenevertheCDS1
inputpinishigh,asshowninFigure10.
• WhenWS=1andCDS=1(CDSmodeonly)
ResetLevelClampingin“WS”modeisonly
possibleinCDSmodeandthetimeatwhichthe
clampswitchisclosedisconcurrentwiththe
referencesampleperiod,C1S,asshowninFigure
11.RLCcanbeenabledonapixelbypixelbasis
undercontroloftheCDS1inputpin.IfCDS1is
highwhenCDS2ishighandissampledbyADCK
thenclampingwillbeenabledforthatinputsample
atthetimedeterminedbyCDSREF[1:0].IfCDS1
islowatthispointthentheRLCswitchwillnotbe
closedforthatinputsample.IfRLCisrequiredon
everypixelthentheCDS1pincanbeconstantly
heldhighin“WS”mode.
Line-clamping (CLPCTL=1)
• WS=0(NormalMode)andCDS=0(Non-CDS
mode)only.
Insituationswheretheinputvideosignaldoesnot
haveastablereferencelevelitmaybenecessary
toclamponlyduringthosepixelswhichhavea
knownstate(e.g.theDummy,orBlackpixelsat
thestartorendofalineofmostimagesensors).
Thisisknownasline-clampingandrelieson
theinputcapacitortoholdtheDClevelbetween
clampintervals.Innon-CDSmode(CDS=0)this
canbedonedirectlybycontrollingtheCDS1
inputpintogohighduringtheblackpixelsonly.
AlternativelyitispossibletouseCDS1toidentify
theblackpixelsandenabletheclampatthesame
timeastheinputisbeingsampled(i.e.whenCDS2
ishighandCDS1ishigh).Thismodeisenabled
bysettingCLPCTL=1andtheoperationisshown
inFigure12.
CDS1
CDS2
ADCK
Analog
Input
CLP
Figure 10 Pixel-Clamping RLC Operation, with CDS (Non-CDS also Possible)
CDS2
ADCK
CDSREF[1:0] = 00
CDSREF[1:0] = 11
CDSREF[1:0] = 10
CDSREF[1:0] = 01
C2S
C2S : Video Sample; C1S : Reference Sample
C1S
C1S
C1S
C1S
CDS1
CDSREF[1:0] = 00
CDSREF[1:0] = 11
CDSREF[1:0] = 10
CDSREF[1:0] = 01
CLP
CLP
CLP
CLP
RLC switch closed when CDS1 = 1
Figure 11 “WS” Mode (WS=1) RLC and Sampling



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