1667C—04/20/11

9DB233

Two Output Differential Buffer for PCIe Gen3

6

Datasheet

Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

-3dB point in High BW Mode

2

2.3

4

MHz

1

-3dB point in Low BW Mode

0.4

0.5

1

MHz

1

PLL Jitter Peaking

Peak Pass band Gain

1

2

dB

1

Duty Cycle

Measured differentially, PLL Mode

45

48

55

%

1

Duty Cycle Distortion

Measured differentially, Bypass Mode @100MHz

-2

1

2

%

1,4

2500

3660

4500

ps

1

-250

0

250

ps

1

Skew, Output to Output

15

50

ps

1

PLL mode

40

50

ps

1,3

Additive

Jitter in Bypass Mode

10

50

ps

1,3

Skew, Input to Output

Jitter, Cycle to cycle

PLL Bandwidth

BW

Electrical Characteristics - PCIe Phase Jitter Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

PCIe Gen 1

32

86

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

1.1

3

ps

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

2.3

3.1

ps

(rms)

1,2

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.5

1

ps

(rms)

1,2,4

PCIe Gen 1

2

5

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.2

0.3

ps

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.8

1

ps

(rms)

1,2

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.1

0.2

ps

(rms)

1,2,4

Phase Jitter, PLL Mode

Additive Phase Jitter,

Bypass Mode