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AD9608 데이터시트(PDF) 13 Page - Analog Devices |
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AD9608 데이터시트(HTML) 13 Page - Analog Devices |
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13 / 40 page ![]() AD9608 Rev. 0 | Page 13 of 40 PIN 1 INDICATOR D6+ D6– D7+ D7– 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK+ CLK– SYNC NC NC NC NC NC NC NC NC NC NC DRVDD NC NC PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR– DRVDD D9+ (MSB) D9– (MSB) D8+ D8– 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9608 INTERLEAVED PARALLEL LVDS TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal). 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16 NC No Connect. Do not connect to this pin. 0 AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. |
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