ANALOG PRODUCTS DIVISION

561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715

www.protekanalog.com

PA5331

Low Power 24-Bit, Stereo Audio CODEC

With Headphone Amplifier

95250 Rev.0. 01/10

NOT FOR USE IN LIFE SUPPORT SYSTEMS

In 2-

wire interface mode, the registers can be written and read. The formats of ―write‖ and ―read‖ instructions are shown in Table 3

and Table 4. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W

to 1 to read data from the register. There are no acknowledge bit after data to be written or read, this is the only difference from the

I

Table 3 Write Data to Register in 2-wire Interface Mode

Chip Address

R/W

Register Address

Data to be written

001000

AD0

0

ACK

RAM

ACK

DATA

Table 4 Read Data from Register in 2-wire Interface Mode

Chip Address

R/W

Register Address

001000

AD0

0

ACK

RAM

Chip Address

R/W

Data to be read

001000

AD0

1

ACK

DATA

CONFIGURATION REGISTER DEFINITION

SPI and 2-wire configuration interface share the same registers because there is only one interface active at any time. There are total

of 53 user programmable 8-bit registers in this device. These registers control the operations of ADC and DAC. External master

controller can access these registers by using the slave address specified in RAM (Register Address Map) register as shown in the

Table 5.

Table 5 Bit Content of Register Address Map

B7

B6

B5

B4

B3

B2

B1

B0

Reg. 00

SCPReset

LRCM

DACMCLK

SameFs

SeqEn

EnRef

VMIDSEL

Reg. 01

TSDEN

PdnOC

LPVcmMod

LPVrefBuf

PdnAna

PdnIbiasgen

VrefrLo

PdnVrefbuf

Reg. 02

adc_DigPDN

dac_DigPDN

adc_stm_rst

dac_stm_rst

ADCDLL_PDN

DACDLL_PDN

adcVref_PDN dacVref_PDN

Reg. 03

PdnAINL

PdnAINR

PdnADCL

PdnADCR

PdnMICB

PdnADCBiasgen

flashLP

int1LP

Reg. 04

PdnDACL

PdnDACR

LOUT1

ROUT1

LOUT2

ROUT2

MONO

OUT3

Reg. 05

LPDACL

LPDACR

LPLOUT1

OC[2]

LPLOUT2

OC[3]

LPMONO

LPOUT3

Reg. 06

LPPGA

LPLMIX

LPRMIX

LPMMIX

LPMOUTINV

LPOUT2INV

LPADCvrp

LPDACvrp

Reg. 07

VSEL

Reg. 08

MSC

MCLKDIV2

BCLK_INV

BCLKDIV

Reg. 09

MicAmpL

MicAmpR

Reg. 10

LINSEL

RINSEL

Reg. 11

DS

MONOMIX

TRI

OC[1:0]

Reg. 12

DATSEL

ADCLRP

ADCWL

ADCFORMAT

Reg. 13

ADCFsMode

ADCFsRatio

Reg. 14

ADC_invL

ADC_invR

ADC_HPF_L

ADC_HPF_R

Reg. 15 ADCRampRate ADCSoftRamp ADCZeroCrs

ADCLeR

ADCMute

Reg. 16

LADCVOL

Reg. 17

RADCVOL

Reg. 18

ALCSEL

MAXGAIN

MINGAIN

Reg. 19

ALCLVL

ALCHLD

Reg. 20

ALCDCY

ALCATK

Reg. 21

ALCMODE

ALCZC

TIME_OUT

WIN_SIZE

Reg. 22

NGTH

NGG

NGAT