전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

PSOT03LC 데이터시트(PDF) 6 Page - Protek Devices

부품명 PSOT03LC
상세설명  500 WATT ULTRA LOW CAPACITANCE TVS ARRAY
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  PROTEC [Protek Devices]
홈페이지  http://www.protekdevices.com
Logo PROTEC - Protek Devices

PSOT03LC 데이터시트(HTML) 6 Page - Protek Devices

  PSOT03LC Datasheet HTML 1Page - Protek Devices PSOT03LC Datasheet HTML 2Page - Protek Devices PSOT03LC Datasheet HTML 3Page - Protek Devices PSOT03LC Datasheet HTML 4Page - Protek Devices PSOT03LC Datasheet HTML 5Page - Protek Devices PSOT03LC Datasheet HTML 6Page - Protek Devices PSOT03LC Datasheet HTML 7Page - Protek Devices PSOT03LC Datasheet HTML 8Page - Protek Devices PSOT03LC Datasheet HTML 9Page - Protek Devices  
Zoom Inzoom in Zoom Outzoom out
 6 / 9 page
background image
Only One Name Means ProTek’Tion™
www.protekdevices.com
05066.R7 9/10
Page 6
PSOT03LC - PSOT36LC
APPLICATION INFORmATION
FIGURE 1 - COmmON mODE I/O PORT PROTECTION
Two PSOTxxLC devices used in parallel. Circuit connectivity is as follows:
• I/O Line connected to Device 1, Pin 1.
• I/O Line connected to Device 2, Pin 2.
• Device 1, Pin 2 connected to ground.
• Device 2, Pin 1 connected to ground.
• Device 1 and 2, Pin 3 not connected.
CIRCUIT BOARD RECOmmENDATIONS
Circuit board layout is critical for electromagnetic compatibility protection. The following guidelines are recommended:
• The protection device should be placed near the input terminals or connectors, the device will divert the transient current
immediately before it can be coupled into the nearby traces.
• The path length between the TVS device and the protected line should be minimized.
• All conductive loops including power and ground loops should be minimized.
• The transient current return path to ground should be kept as short as possible to reduce parasitic inductance.
• Ground planes should be used whenever possible. For multilayer PCBs, use dedicated ground planes
2
3
1
2
3
1
I/O LINE
GND
2
3
1
2
3
1
I/O 1
I/O 2
FIGURE 1 - DIFFERENTIAL mODE EThERNET PROTECTION
Two PSOTxxLC devices used in parallel. Circuit connectivity is as follows:
• I/O Line 1 connected to Device 1, Pin 1.
• I/O Line 1 connected to Device 2, Pin 2.
• I/O Line 2 connected to Device 1, Pin 1.
• I/O Line 2 connected to Device 2, Pin 2.
• Device 1 and 2, Pin 3 not connected.



Html Pages

1 2 3 4 5 6 7 8 9


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com