Integrating SMT Synthesizer Solutions into Wireless Designs

Rev. V2

Application Note

AN3003

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Clock, Data and Load Enable Inputs

The Clock, Data and Load Enable Inputs are all high

impedance CMOS and should be fed with square

waves with level of VHIGH ³ 0.8 Vcc and VLOW £

0.2 Vcc. An external termination resistor can be

added externally if desired.

Refer to the specific

device datasheet for the proper programming infor-

mation.

Consideration needs to be taken when

choosing the command word for programming the

dividers. While the PLL will allow for a variety of

steps to be programmed, the step size specific to

the synthesizer design should be used. The internal

loop filter is optimized for a given step size and the

use of another could result in greater than specified

phase noise or spurious outputs.

Noise Contributors

Understanding the key contributors to single side-

band phase noise is paramount to achieving opti-

mum performance. Often, the noise profile can be

adjusted to obtain dynamic properties of the synthe-

sizer. Careful consideration of the noise profile re-

quired at spot frequencies, integrated or both will

lead to a superior system design. Phase noise is

measured in units of dBc/Hz at a given offset from

the carrier. It is the difference between the level of

the carrier and the noise level at a given offset nor-

malized to a 1Hz bandwidth.

Assuming power supply contribution is negligible,

the three key contributors are:

• Phase Comparator Noise

• Reference Noise

• VCO Noise

The phase comparator noise affects the noise floor

within the loop. The phase noise is multiplied up to

other effect that is often ignored is that the noise

floor is related to the step size by approximately

10dB/decade. This is particularly important as the

step size is increased because the noise floor de-

frequency at which the noise floor is measured.

For example consider a PLL IC which has a noise floor

of approximately –165 dBc/Hz at a phase comparison

frequency of 30 kHz. If the frequency output of the

synthesizer is 1 GHz with a step size of 200 kHz the

noise floor within the loop is:

= -165 + 10 log (200 kHz/30 kHz)

+ 20 log (1 GHz/200 kHz) = -82.78 dBc/Hz

With respect to the effect of the reference noise, the

reference frequency is multiplied up to the VCO output

frequency within the PLL IC. The noise side bands of

the reference oscillator are increased by the ratio given

by 20log(FVCO/Fref).

For example, a synthesizer with a 15 MHz reference is

divided down to 30 kHz has an output frequency of

1GHz. If the 15 MHz reference noise is –115 dBc/Hz at

100 Hz offset, then the reference noise at the output

frequency would be:

-115 +20 log (1 GHz / 15 MHz) = -78.5 dBc/Hz

Finally the effect of the VCO noise should be consid-

ered. Within the loop bandwidth, the VCO noise is

suppressed at a rate of –40 dB/decade. Near the loop

bandwidth, the suppression is not so great and some of

the VCO noise will add to the loop noise floor. Spurious

signals that are at or within the loop bandwidth will

undergo similar suppression characteristics to phase

noise. Figure 4 gives a good representation of this

effect when trying to assess design risks.

Ultimately the VCO design is part of the integrated

package so outside the scope of changes to the

synthesizer interfaces but as noise that appears on the

power supplies modulates the VCO this will directly

effect the performance of the synthesizer. The same

principles as described earlier should be applied to

reduce power supply noise.

Loop

VCO (suppressed)

Reference

VCO

Loop (suppressed)

Reference (suppresed)

F/2

F

2F

Sideband Frequency

Figure 4