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SC508 데이터시트(PDF) 18 Page - Semtech Corporation

부품명 SC508
상세설명  EcoSpeed짰 DC-DC Buck Controller with Integrated LDO
PDF  32 Pages
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제조업체  SEMTECH [Semtech Corporation]
홈페이지  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC508 데이터시트(HTML) 18 Page - Semtech Corporation

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SC508/SC508A
18
The current limit schematic with the R
LIM resistor is shown
in Figure 10.
VOUT
VIN
+
CIN
Q2
+
D2
RLIM
CBST
Q1
L
PGND
DL
ILIM
LX
DH
BST
COUT
Figure 10 — Valley Current Limit
Setting the valley current limit to 10A results in a peak
inductor current of 10A plus peak ripple current. In this
situation the average current through the inductor is 10A
plus one-half the peak-to-peak ripple current.
The R
LIM value is calculated by the next equation.
The internal 10μA current source is temperature compen-
sated at 4100ppm in order to provide tracking with the
RDS
ON.
Soft-Start of PWM Regulator
The SC508 has a programmable soft-start time that is con-
trolled by an external capacitor at the SS pin. During the
soft-start time, the controller sources 3μA from the SS pin
to charge the capacitor. During the start-up process
(Figure 11), 40% of the voltage ramp at the SS pin is used
as the reference for the FB comparator. The PWM compara-
tor issues an on-time pulse when the FB voltage is less
than 40% of the SS voltage, which forces the output
voltage to follow the SS ramp. The output voltage reaches
regulation when the SS pin voltage exceeds 1.5V and the
FB reaches the 600mV threshold. The time between the
first LX pulse and VOUT reaching the regulation point is
the soft-start time (t
SS). The calculation for the soft-start
time is shown by the following equation.
A
3
V
5
.
1
C
t
SS
SS
After the SS capacitor voltage reaches 1.5V, the SS capaci-
tor continues to charge until the SS voltage is equal to
67% of VDDA. At this time the Power Good monitor com-
pares the FB pin and sets the PGOOD output high (open
drain) if VOUT is in regulation. The time between VOUT
reaching the regulation point and the PGOOD output
going high is shown by the following equation.
The time from the rising edge of the EN pin to the PGOOD
output going high is shown by the following equation.
After the Power Good Start-up Delay Time is completed,
the SS pin is internally pulled up to the VDDA supply.
The soft-start cycle and Power Good timing can be seen in
the Figure 11.
EN
SS
FB
PGOOD
CSS charging
current 3uA
VSS = 1.5V
VOUT in regulation
VSS = 3.35V
tSS
tPGOOD
Figure 11 — Soft-start Cycle and Power Good timing
Applications Information (continued)



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