R5F52105ADFN datasheet(49/146 Pages) RENESAS

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R01DS0041EJ0090 Rev.0.90

Page 49 of 144

Aug 10, 2011

RX210 Group

2. CPU

Under development Preliminary document

Specifications in this document are tentative and subject to change.

2.8.2

Instructions and Pipeline Processing

The operands in the table below indicate the following meaning.

#IMM: Immediate

Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register, CR: Control register

dsp: dsp5, dsp8, dsp16, dsp24

pcdsp: pcdsp3, pcdsp8, pcdsp16, pcdsp24

2.8.2.1

Instructions Converted into Single Micro-Operation and Pipeline Processing

The table below lists the instructions that are converted into a single micro-operation. The number of cycles in the table

indicates the number of cycles during no-wait memory access.

Note 1. The number of cycles for the dividing instruction varies according to the divisor and dividend.

Note 2. For the number of cycles for throughput and latency, see section 2.8.3, Calculation of the Instruction Processing Time.

Table 2.13

Instructions that are Converted into a Single Micro-Operation

Instruction

Mnemonic (indicates the common operation when

the size is omitted)

Reference

Figure

Number of

Cycles

Arithmetic/logic instructions

(register-register, immediate-register)

Except EMUL, EMULU, RMPA, DIV,

DIVU and SATR

 {ABS, ADC, ADD, AND, CMP, MAX, MIN, MUL, NEG,

NOP, NOT, OR, ROLC, RORC, ROTL, ROTR, SAT, SBB,

SHAR, SHLL, SHLR, SUB, TST, XOR} “#IMM, Rd”/“Rd”/

“Rs, Rd”/“Rs, Rs2, Rd”

Figure 2.10

Arithmetic/logic instructions (division)

 DIV “#IMM, Rd”/“Rs, Rd”

Figure 2.10

3 to 20*1

 DIVU “#IMM, Rd”/“Rs, Rd”

Figure 2.10

2 to 18*1

Data transfer instructions

(register-register, immediate-register)

 {MOV, MOVU, REVL, REVW} “#IMM, Rd”/“Rs, Rd”

 SCCnd “Rd”

 {STNZ, STZ} “#IMM, Rd”

Figure 2.10

Transfer instructions (load operation)

 {MOV, MOVU} “[Rs], Rd”/“dsp[Rs], Rd”/“[Rs+], Rd”/

“[–Rs], Rd”/“Rs, [Ri, Rb]”

 POP “Rd”

Figure 2.11

Throughput: 1

Latency: 2*2

Transfer instructions (store operation)

 MOV “Rs, [Rd]”/“Rs, dsp[Rd]”/“Rs, [Rd+]”/“Rs, [–Rd]”/

“Rs, [Ri, Rb]”

 PUSH “Rs”

 PUSHC “CR”

Figure 2.12

Bit manipulation instructions (register)

 {BCLR, BNOT, BSET, BTST} “#IMM, Rd”/“Rs, Rd”

 BMCnd “#IMM, Rd”

Figure 2.10

Branch instructions

 BCnd “pcdsp”

 {BRA, BSR} “pcdsp”/“Rs”

 {JMP, JSR} “Rs”

Figure 2.20

Branch taken: 3

Branch not

taken: 1

System manipulation instructions

 CLRPSW, SETPSW “#IMM”

 MVTC “#IMM, CR”/“Rs, CR”

 MVFC “CR, Rd”

 MVTIPL“#IMM”

—1

DSP instructions

 {MACHI, MACLO, MULHI, MULLO} “Rs, Rs2”

 {MVFACHI, MVFACMI} “Rd”

 {MVTACHI, MVTACLO} “Rs”

 RACW“#IMM”

Figure 2.10

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