8565L-S08-R datasheet(12/13 Pages) UTC

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8565

Preliminary

LINEAR INTEGRATED CIRCUIT

UNISONICTECHNOLOGIESCO.,LTD

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www.unisonic.com.tw

QW-R114-004.b

FUNCTIONAL DESCRIPTION(Cont.)

8.2 Enhanced Dynamic Response

Due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about

several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the

event of heavy load changes.

The IC provides therefore a “window detector” for the feedback voltage VVSENSE at pin 1 (VSENSE). Whenever

VVSENSE exceeds the reference value (5V) by ±5%, it will act on the nonlinear gain block which in turn affect the gate

drive duty cycle directly. This change in duty cycle is bypassing the slow changing VCOMP voltage, thus results in a

fast dynamic response of VOUT.

9. Output Gate Driver

The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a

Zener diode Z1 (see Fig. 15) to protect the external transistor switch against undesirable over voltages. The

maximum voltage at pin 7 (GATE) is typically clamped at 11.5V.

The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive is

internally pull low to maintain the off state.

TYPICAL APPLICATION CIRCUIT

85...265VAC EMI-Filter

SWITCH

Auxiliary Supply

VCC

PFC-Controller

Protection Unit

Voltage Loop

Compensation

PWM Logic

Driver

Variable

Oscillator

Ramp

Generator

Nonlinear

Gain

Current Loop

Compensation

ISENSE

GATE

FREQ

ICOMP

VOUT

VSENSE

VCOMP

GND

UTC 8565

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