74HC4066 datasheet(2/27 Pages) PHILIPS

2 / 27 page

2004 Nov 11

Philips Semiconductors

Product speciﬁcation

Quad bilateral switches

74HC4066; 74HCT4066

FEATURES

• Very low ON-resistance:

–50

Ω (typical) at VCC = 4.5 V

–45

Ω (typical) at VCC = 6.0 V

–35

Ω (typical) at VCC = 9.0 V.

• Complies with JEDEC standard no. 7A

• ESD protection:

HBM EIA/JESD22-A114-B exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 °C to +85 °C and −40 °C to +125 °C.

GENERAL DESCRIPTION

The 74HC4066 and 74HCT4066 are high-speed Si-gate

CMOS devices and are pin compatible with the

HEF4066B. They are specified in compliance with JEDEC

standard no. 7A.

The 74HC4066 and 74HCT4066 have four independent

analog switches. Each switch has two input/output pins

(pins nY or nZ) and an active HIGH enable input pin

(pin nE). When pin nE = LOW the belonging analog switch

is turned off.

The 74HC4066 and 74HCT4066 are pin compatible with

the 74HC4016 and 74HCT4016 but exhibit a much lower

on-resistance. In addition, the on-resistance is relatively

constant over the full input signal range.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ[(CL +CS) × VCC2 × fo] where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

CS = maximum switch capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

Σ[(CL +CS) × VCC2 × fo] = sum of the outputs.

2. For 74HC4066 the condition is VI = GND to VCC.

For 74HCT4066 the condition is VI = GND to VCC − 1.5 V.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

74HC4066

74HCT4066

tPZH/tPZL

turn-on time nE to Vos

CL = 15 pF; RL =1kΩ; VCC = 5 V 1112ns

tPHZ/tPLZ

turn-off time nE to Vos

CL = 15 pF; RL =1kΩ; VCC = 5 V 1316ns

input capacitance

3.5

CPD

power dissipation

capacitance per switch

notes 1 and 2

maximum switch

capacitance

88pF

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