ADM2914

Rev. B | Page 13 of 16

OV LATCH (ADM2914-1)

If an overvoltage condition occurs when the LATCH pin is

pulled low, the OV pin latches low. Pulling LATCH high clears

the latch. If an OV condition clears while LATCH is high, the

latch is bypassed and the OV pin behaves in the same way as the

UV pin, with an identical timeout period. If the LATCH pin is

pulled low while the timeout period is active, the OV pin

latches low, as in normal operation.

DISABLE (ADM2914-2)

Pulling the DIS pin high disables both the UV and OV outputs,

and forces both outputs to remain weakly pulled high, regard-

less of any faults that are detected at the inputs. If a UVLO

condition is detected, the UV output is asserted and pulls low;

however, the timeout function is bypassed. As soon as the

UVLO condition clears, the UV output pulls high. To guarantee

normal operation when the pin is left unconnected, DIS has a

weak 2 μA internal pull-down current.