AD6657ABBCZ datasheet(35/36 Pages) AD

35 / 36 page

Data Sheet

AD6657A

Rev. 0 | Page 35 of 36

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting the design and layout of the AD6657A in a

system, it is recommended that the designer become familiar

with these guidelines, which discuss the special circuit

connections and layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD6657A, it is recommended

that two separate 1.8 V supplies be used. Use one supply for

analog (AVDD); use a separate supply for the digital outputs

(DRVDD). The AVDD and DRVDD supplies should be isolated

with separate decoupling capacitors. Several different decoupling

capacitors can be used to cover both high and low frequencies.

Locate these capacitors close to the point of entry at the PCB

level and close to the pins of the part, with minimal trace length.

A single PCB ground plane is sufficient when using the AD6657A.

With proper decoupling and smart partitioning of the PCB

analog, digital, and clock sections, optimum performance is

easily achieved.

VCMx Pins

The VCMx pins are provided to set the common-mode level

of the analog inputs. Decouple the VCMx pins to ground with a

0.1 μF capacitor, as shown in Figure 37.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the AD6657A is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade AD6657A performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the AD6657A to prevent these signals from transi-

tioning at the receiver inputs during critical sampling periods.

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