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AD6672 데이터시트(PDF) 9 Page - Analog Devices

부품명 AD6672
상세설명  IF Receiver
PDF  32 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD6672 데이터시트(HTML) 9 Page - Analog Devices

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AD6672
Rev. 0 | Page 9 of 32
TIMING SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SPI TIMING REQUIREMENTS
See Figure 42 for the SPI timing diagram
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
Minimum period that SCLK should be in a logic high state
10
ns
tLOW
Minimum period that SCLK should be in a logic low state
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 42)
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 42)
10
ns



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