ADE7880 datasheet(89/104 Pages) AD

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Data Sheet

ADE7880

Rev. A | Page 89 of 104

Address

R/W1

Bit

Length

Bit Length

During

Communication2

Type3

Default

Value4

Description

computations.

0xEA0B to

0xEBFE

Reserved

Reserved. These registers are always 0.

0xEBFF

Reserved

This address can be used in manipulating

the SS/HSA pin when SPI is chosen as

the active port. See the

section for details.

Serial Interfaces

0xEC00

LPOILVL

R/W

0x07

Overcurrent threshold used during

PSM2 mode. See Table 55 in which the

0xEC01

CONFIG2

R/W

0x00

Configuration register used during

PSM1 mode. See Table 56.

1 R is read, and W is write.

2 32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that

is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.

3 U is unsigned register, and S is signed register in twos complement format.

4 N/A is not applicable.

Table 34. IPEAK Register (Address 0xE500)

Bit

Mnemonic

Default Value

Description

23:0

IPEAKVAL[23:0]

These bits contain the peak value determined in the current channel.

IPPHASE[0]

When this bit is set to 1, Phase A current generated IPEAKVAL[23:0] value.

IPPHASE[1]

When this bit is set to 1, Phase B current generated IPEAKVAL[23:0] value.

IPPHASE[2]

When this bit is set to 1, Phase C current generated IPEAKVAL[23:0] value.

31:27

00000

These bits are always 0.

Table 35. VPEAK Register (Address 0xE501)

Bit

Mnemonic

Default Value

Description

23:0

VPEAKVAL[23:0]

These bits contain the peak value determined in the voltage channel.

VPPHASE[0]

When this bit is set to 1, Phase A voltage generated VPEAKVAL[23:0] value.

VPPHASE[1]

When this bit is set to 1, Phase B voltage generated VPEAKVAL[23:0] value.

VPPHASE[2]

When this bit is set to 1, Phase C voltage generated VPEAKVAL[23:0] value.

31:27

00000

These bits are always 0.

Table 36. STATUS0 Register (Address 0xE502)

Bit

Mnemonic

Default Value

Description

AEHF

When this bit is set to 1, it indicates that Bit 30 of any one of the total active energy

registers (AWATTHR, BWATTHR, or CWATTHR) has changed.

FAEHF

When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental active

energy registers, FWATTHR, BFWATTHR, or CFWATTHR, has changed.

Reserved

This bit is always 0.

FREHF

When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental

reactive energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed.

VAEHF

When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy

registers (AVAHR, BVAHR, or CVAHR) has changed.

LENERGY

When this bit is set to 1, in line energy accumulation mode, it indicates the end of an

integration over an integer number of half line cycles set in the LINECYC register.

REVAPA

When this bit is set to 1, it indicates that the Phase A active power identified by Bit 6

(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The

sign itself is indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 46).

REVAPB

When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6

(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The

sign itself is indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 46).

REVAPC

When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6

(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The

sign itself is indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 46).

ADE7880 데이터시트(PDF) 89 Page - Analog Devices

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