ADP2370ACPZ-5.0-R7 datasheet(20/32 Pages) AD

20 / 32 page

ADP2370/ADP2371

Data Sheet

Rev. A | Page 20 of 32

THEORY OF OPERATION

SLOPE COMP

OSCILLATOR

DEFAULT = 1.2MHz

VOUT ÷ 2 FREQUENCY

FOLDBACK

CONTROL

LOGIC

ADP2371

ONLY

SOFT

START

1.2V

VIN

PGND

SYNC

FSEL

1.0V

STANDBY

EN_PREC

VIN

200mA

UVLO

VIN

PWM

PSM

0.808V

0.8V

VIN

1.2A

VIN

REG

VIN

2.95V

0.736V

0.8V

0.696V

150°C

135°C

H = FPWM

L = PWM/PSM

H = 1.2MHz

L = 600kHz

THSD

ISLOPE

RDSON × Kr

P_ILIMIT

N_ILIMIT

–0.5A – (PWM)

0A – (PSM)

IMIN

VSW

VCOMP

ICOMP

VTOL

Figure 71. Functional Block Diagram

The ADP2370/ADP2371 use a high speed, current mode, con-

stant frequency PWM control scheme for excellent stability and

transient response. To ensure the longest battery life in portable

applications, the ADP2370/ADP2371 has a power saving mode.

Under light load conditions, the output capacitor is charged as

needed to maintain regulation; otherwise, the ADP2370/ADP2371

enter sleep mode, a low 14 μA quiescent state. The architecture

ensures smooth transitions from PWM mode to and from PSM,

and maintains high efficiencies at light loads. The following sec-

tions describe the two modes of operation and provide detailed

descriptions of the ADP2370/ADP2371 features.

PWM OPERATION

The ADP2370/ADP2371 PWM mode is a fixed frequency,

1.2 MHz typical, current mode architecture. Use the SYNC pin

to synchronize the regulator to an external clock frequency or

use the FSEL pin to select an internal clock frequency of

600 kHz or 1.2 MHz.

The ADP2370/ADP2371 use a constant slope compensation

scheme where the inductor scales with the output voltage. The

equation for choosing the inductor for a particular output

voltage is

OUT

478

See the Applications Information section for details regarding

choosing an appropriate inductor value.

Cycle to cycle operation of the PWM mode begins with the

falling edge of the internal clock. Note that when using an

external clock, the rising edge synchronizes the regulator and

the falling edge is determined by the internal clock, typically a

25 ns pulse width. The falling edge of the clock starts the cycle

by turning on the high-side switch, which produces a positive

di/dt current in the inductor. The PWM comparator controls

when the high-side switch turns off. The positive input of the

comparator monitors the peak inductor current via the SW node.

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