OSC

Q

Q

SN6501

Gate

Drive

D1

V

CC

D2

GND

GND

1

5

2

3

4

D1

V

CC

D2

GND

GND

50W

10µF

3

1

SN6501

5

2

4

D2

D1

GND

GND

50W

1

5

4

3

10µF

0.1µF

V

IN

10µF

MBR0520L

MBR0520L

T1

10µF

3

1

SN6501

5

2

4

LDO

2

TP1

TP2

V

OUT

0.1µF

D2

D1

V

CC

GND

GND

IN

EN

NC

OUT

GND

SN6501

SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

PIN FUNCTIONS

PIN No.

NAME

DESCRIPTION

1

D1

Drain 1

2

Vcc

Supply voltage

3

D2

Drain 2

4,5

GND

Ground

TEST CIRCUIT

Figure 3. Test Circuit for Output Voltage and Efficiency at TP1 and TP2

(see Figure 4 to Figure 23)

2

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