LTM9002 datasheet(13/32 Pages) LINER

13 / 32 page

LTC2159

2159f

pin FuncTions

FULL RATE CMOS OUTPUT MODE

All Pins Below Have CMOS Output Levels (OGND to

OVDD)

D0 to D15 (Pins 21-28, 33-40): Digital Outputs. D15 is

the MSB.

CLKOUT– (Pin 29): Inverted version of CLKOUT+.

CLKOUT+ (Pin 30): Data Output Clock. The digital outputs

normally transition at the same time as the falling edge

of CLKOUT+. The phase of CLKOUT+ can also be delayed

relative to the digital outputs by programming the mode

control registers.

DNC (Pin 41): Do not connect this pin.

OF(Pin42):Overflow/UnderflowDigitalOutput.OFishigh

when an overflow or underflow has occurred.

DOUBLE DATA RATE CMOS OUTPUT MODE

All Pins Below Have CMOS Output Levels (OGND to

OVDD)

D0_1 to D14_15 (Pins 22, 24, 26, 28, 34, 36, 38, 40):

Double Data Rate Digital Outputs. Two data bits are mul-

tiplexed onto each output pin. The even data bits (D0,

D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+

is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13,

D15) appear when CLKOUT+ is high.

DNC (Pins 21, 23, 25, 27, 33, 35, 37, 39, 41): Do not

connect these pins.

CLKOUT– (Pin 29): Inverted version of CLKOUT+.

CLKOUT+ (Pin 30): Data Output Clock. The digital outputs

normally transition at the same time as the falling and ris-

ing edges of CLKOUT+. The phase of CLKOUT+ can also

be delayed relative to the digital outputs by programming

the mode control registers.

OF(Pin42):Overflow/UnderflowDigitalOutput.OFishigh

when an overflow or underflow has occurred.

DOUBLE DATA RATE LVDS OUTPUT MODE

All Pins Below Have LVDS Output Levels. The Output

Current Level is Programmable. There is an Optional

Internal 100Ω Termination Resistor Between the Pins

of Each LVDS Output Pair.

D0_1–/D0_1+ to D14_15–/D14_15+ (Pins 21/22, 23/24,

25/26, 27/28, 33/34, 35/36, 37/38, 39/40): Double Data

Rate Digital Outputs. Two data bits are multiplexed onto

each differential output pair. The even data bits (D0, D2,

D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low.

The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15)

appear when CLKOUT+ is high.

CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock.

The digital outputs normally transition at the same time

as the falling and rising edges of CLKOUT+. The phase of

CLKOUT+ can also be delayed relative to the digital outputs

by programming the mode control registers.

OF–/OF+(Pins41/42):Overflow/UnderflowDigitalOutput.

OF+ is high when an overflow or underflow has occurred.

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