LTC2913 datasheet(10/16 Pages) LINER

10 / 16 page

LTC2960

2960f

APPLICATIONS INFORMATION

provide effective pull-down without excessively loading the

pull-up circuitry. A 100k resistor from output to ground is

satisfactory for most applications. When the status outputs

are high, power is dissipated in the pull-down resistors.

If VCC falls below the falling UVLO threshold, the outputs

are pulled to ground. The outputs are guaranteed to stay

low for VCC ≥ 1.2Vregardless of the output logic configura-

tion. When VCC < 1.2V, the active pull-up output behaves

similarly to an open-drain output with a pull-up resistor.

and MR is a solution to this issue. The MR input can be

pulled to 36V maximum and will not affect the internal

circuitry. Input MR is often pulled down through the use

of a pushbutton switch.

SELECTING THE RESET TIMEOUT PERIOD

Use the RT input (LTC2960-1/ LTC2960-2) to select between

two fixed reset timeout periods. Connect RT to ground for

a 15ms timeout. Connect RT to VCC for a 200ms timeout.

The reset timeout period occurs after the ADJ input is

driven above threshold and the MR input transitions above

its logic threshold. After the reset timeout period, the RST

output is allowed to pull up to a high state as shown in

Figure 5. The RT input is replaced by the DVCC input in

the LTC2960-3/LTC2960-4 options and the reset timeout

period defaults to 200ms.

0.4V

IN+

LTC2960-3

(a). PUSH-PULL CONFIGURATION

(b). OPEN-DRAIN CONFIGURATION

DVCC

1.6V TO 5.5V

6.3V MAX

OUT

LTC2960-3

DVCC

OUT

–

0.4V

IN+

–

2960 F04

Figure 4. LTC2960-3 (LTC2960-4) RST and OUT Outputs are

Configurable as Push-Pull or Open-Drain

ADJ

15ms

200ms

2960 F05

RST, RT = GND

RST, RT = VCC

Figure 5. Selectable Reset Timeout Period

MANUAL RESET INPUT

When ADJ is above its reset threshold and the manual

reset input (MR) is pulled low, the RST output is forced

low. RST remains low for the selected reset timeout period

after the manual reset input is released and pulled high.

The manual reset input is pulled up internally through a

1μA current source to an internal bias voltage (see Elec-

trical Characteristics). If external leakage currents have

the ability to pull down the manual reset input below its

logic threshold, a pull-up resistor placed between VCC

EXTERNAL HYSTERESIS

The LTC2960 IN+ comparator hysteresis is 20mV (V+HYS),

or 5% referred to VTH. Certain applications require more

than the built-in native hysteresis. The application sche-

matic in Figure 6 adds one additional resistor (R6) to a

typical attenuator network. The procedure below is used

to determine a value for R6 to provide an increase over

the native hystereis. In this example, it is desired to double

the native hysteresis from 300mV to 600mV and achieve

a falling threshold of 6V.

Before including R6, the rising threshold (VR) is 6.293V

while the falling threshold (VF) is 5.993V. The hysteresis

referred to VA is calculated from:

VHYST VA

() = VPHYS 1+

⎛

⎝⎜

⎞

⎠⎟ =

20mV

•15 = 300mV

LTC2913 데이터시트(PDF) 10 Page - Linear Technology

LTC2913 데이터시트(HTML) 10 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

데이터시트 다운로드

링크 URL