MMA6519KW datasheet(52/56 Pages) FREESCALE

52 / 56 page

Sensor

Freescale Semiconductor, Inc.

MMA65xx

4.5.5

Internal Error

The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register:

•

OTP CRC Failure

•

Writable Register CRC Failure

•

Self Test Error

•

Invalid internal logic states

4.5.5.1

CRC Error

If the IDE bit is set in the DEVSTAT register due to one or more of the following errors, the device will respond to acceleration

data requests with an “Internal Error Present” response until the IDE bit is cleared in the DEVSTAT register.

•

An OTP Shadow Register CRC failure as described in Section 3.2

•

A Writable Register CRC failure as described in Section 3.2

•

A clock monitor CRC failure as described in Section 3.4.2

The arming function will not be updated on Acceleration Data Request commands if a CRC Error is detected. The PCM output

is not affected by the CRC error.

If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only

be cleared by a device reset. The IDE bit will not be cleared on a read of the DEVSTAT register.

If the CRC error is in the OTP shadow register array, the error cannot be cleared.

4.5.5.2

Self Test Error

If the IDE bit is set in the DEVSTAT register due to a Self Test activation failure, the device will respond to acceleration data

requests with a “Self Test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be

updated on Acceleration Data Request commands if a Self Test Error is detected. The PCM output is not affected by the Self Test

Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal failure

is removed. If the internal error is still present when the DEVSTAT register is read, the IDE bit will remain set.

4.5.6

Offset Monitor Error

If an offset monitor error is present as described in Section 3.8.5, the OFFSET_X or OFFSET_Y bit in the DEVSTAT register

will be set. The device will respond to an acceleration request for the corresponding axis with an “Internal Error Present” response

until the OFFSET_X or OFFSET_Y bit is cleared in the DEVSTAT register. The arming function will not be updated. Once the

error condition is removed, the OFFSET_X or OFFSET_Y bit in the DEVSTAT register will remain set until a read of the DEVSTAT

The PCM output is not affected by the offset monitor over range condition.

4.6

Initialization SPI Response

The first data transmitted by the device following reset is the SPI Error response shown in Table 30. This ensures that an un-

expected reset will always be detectable. The device will respond to all acceleration data requests with the “Invalid Acceleration

Data Request” response until the DEVRES bit in the DEVSTAT register is cleared via a read of the DEVSTAT register. The arming

function will not be updated on Acceleration Data Request commands until the DEVRES bit in the DEVSTAT register is cleared.

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