| 전자부품 데이터시트 검색엔진 |
|
MPC8377E 데이터시트(PDF) 49 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8377E 데이터시트(HTML) 49 Page - Freescale Semiconductor, Inc |
|
49 / 127 page ![]() MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8 Freescale Semiconductor 49 11.2.2.2 Full-Speed Read Meeting Hold (Minimum Delay) There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data. tCLK_DELAY + tOH + tDATA_DELAY > tSFSIXKH Eqn. 9 This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled. 11.3 eSDHC AC Timing Specifications (High-Speed Mode) This table provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 30 and Figure 31. Table 43. eSDHC AC Timing Specifications for High-Speed Mode At recommended operating conditions OVDD = 3.3 V ± 165 mV. Parameter Symbol1 Min Max Unit Note SD_CLK clock frequency—high speed mode fSHSCK 050 MHz — SD_CLK clock cycle tSHSCK 20 — ns — SD_CLK clock frequency—identification mode fSIDCK 0400 KHz — SD_CLK clock low time tSHSCKL 7— ns 2 SD_CLK clock high time tSHSCKH 7— ns 2 SD_CLK clock rise and fall times tSHSCKR/ tSHSCKF —3 ns 2 Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIVKH 5— ns 2 Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIXKH 0— ns 2 Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV —4 ns 2 Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid tSHSKHOX 0— ns 2 SD_CLK delay within device tINT_CLK_DLY 1.5 — ns 4 SD Card Input Setup tISU 6— ns 3 SD Card Input Hold tIH 2— ns 3 SD Card Output Valid tODLY —14 ns 3 SD Card Output Hold tOH 2.5 — ns 3 Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Measured at capacitive load of 40 pF. 3. For reference only, according to the SD card specifications. 4. Average, for reference only. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |