MPC8378E datasheet(85/128 Pages) FREESCALE

85 / 128 page

MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This figure shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with device SerDes reference clock

input’s DC requirement.

Figure 59. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

This figure shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common-mode voltage is higher than the device SerDes reference clock input’s

allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS

output driver features a 50-

Ω termination resistor. It also assumes that the LVDS transmitter establishes its

own common mode level without relying on the receiver or other external component.

Figure 60. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 61 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

device SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 61 assumes

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

Clock driver vendor dependent

source termination resistor

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

HCSL CLK Driver Chip

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

Chip

CLK_Out

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVDS CLK Driver Chip

10 nF

Chip

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