MPC8379E datasheet(49/117 Pages) FREESCALE

49 / 117 page

MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This figure provides the eSDHC clock input timing diagram.

Figure 29. eSDHC Clock Input Timing Diagram

11.3.1

High-Speed Output Path (Write)

This figure provides the data and command output timing diagram.

Figure 30. High Speed Output Path

11.3.1.1

High-Speed Write Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

Zero clock delay:

tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL

Eqn. 10

With clock delay:

tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL + tCLK_DELAY

Eqn. 11

tDATA_DELAY – tCLK_DELAY < tSHSCKL – tISU – tSHSKHOV

Eqn. 12

eSDHC

tSHSCKR

External Clock

tSHSCK

tSHSCKF

VM = Midpoint Voltage (OVDD/2)

operational mode

tSHSCKL

tSHSCKH

Output valid time: tSHSKHOV

Output hold time: tSHSKHOX

tIH (2 ns)

tCLK_DELAY

Input at the

SD CLK at

Driving

Edge

Sampling

edge

the card Pin

SD card pins

tISU (6 ns)

tDATA_DELAY

tSHSCKL

tSHSCK (clock cycle)

SD CLK at the

MPC8379E pin

Output from the

MPC8379E pins

MPC8379E 데이터시트(PDF) 49 Page - Freescale Semiconductor, Inc

MPC8379E 데이터시트(HTML) 49 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL