HS3140 datasheet(6/7 Pages) SIPEX

6 / 7 page

HS3140/SP7514

HS3140/SP7514 14-Bit Multiplying DACs

Figure 4. Microprocessor Interface to SP7514/HS3140

CLK

74273

VREF

(+ 25V MAX)

LSB

SP7514/

7516

74273

CLK

MSB GND

LATCHES

ADDRESS DECODER

G2A

74LS138

G2B

–

200

470

400

BDSEL

A 2

A 1

A 0

VREF

VDD

I01

I02

UNIPOLAR MODE

(2-QUADRANT)

VOUT

0 TO - V REF

(1-2 - N)

R0S

Resistor R

p can be added, this will parallel Rj decreas-

ing the effective resistance. If C

f is reduced the

bandwidth will be increased and settling time de-

creased. However a system penalty for lowering C

f is

to increase noise gain. The trade-off is noise vs.

settling time. If R

p is added then a large value (1µF or

greater) non-polarized capacitor C

p should be added

in series with R

p to eliminate any DC drifts. If settling

time is not important, eliminate R

p and Cp, and adjust

f to prevent overshoot.

Output Offset

In most applications, the output of the DAC is fed into

an amplifier to convert the DAC’s current output to

voltage. A little known and not commonly discussed

parameteristhelinearityerrorversusoffsetvoltageof

the output amplifier. All CMOS DAC’s must operate

into a virtual ground, i.e., the summing junction of an

opamp.Anyamplifier’soffsetfromtheamplifierwill

appear as an error at the output (which can be related

to LSB’s of error).

MostallCMOSDAC’scurrentlyavailableareimple-

mented using an R-2R ladder network. The formula

for nonlinearity is typically 0.67mV/mV

OS (not de-

rived here). However the SP7516 has a coefficient of

only 0.065mV/mVOS. This is due to the decoding

technique described earlier. CMOS DAC applica-

tions notes (including this one) always show a poten-

tiometer used to null out the amplifier’s offset. If an

amplifier is chosen having ‘pretrimmed’ offset it may

be possible to eliminate this component. Consider the

following calculations:

SP7514/

HS3140

1. Using LF441A amplifier (low power - 741 pinout)

2. Specified offset: 0.5mV max

3. Temperature coefficient of input offset: 10

µV/°Cmax

OS max (0°C to 70°C)

= 0.5mV + (70

µV)10

= 1.2mV

Add'l nonlinearity (max.) = 1.2mV x 0.065mV/mV

µV (1/2 LSB @ 16 Bits)

Where: 78

µV = 1/2 LSB @ 16 Bits (10V range)

Via the above configuration, the SP7514/HS3140

can be used to divide an analog signal by digital code

(i.e. for digitally controlled gain). The transfer func-

tion is given in Table 2, where the value of each bit is

0or1.Divisionbyall“0”sisundefinedandcausesthe

op amp to saturate.

Applications Information

Unipolar Operation

Figure 2 shows the interconnections for unipolar

operation. Connect I

O1 and FB1 as shown in diagram.

TieI

O2 (Pin 7), FB3 (Pin 3), and FB4 (Pin 1) to Ground

(Pin8).Asshown,aseriesresistorisrecommendedin

the V

DD supply line to limit current during ‘turn-on’.

To maintain specified linearity, external amplifiers

must be zeroed. Apply an ALL “ZEROES” digital

input and adjust R

OS for VOUT = 0 ± 1mV.

The

SP7514 and HS3140 have been used successfully

with OP-07, OP-27 and LF441A. For high speed

applications the SP2525 is recommended.

Bipolar Operation

Figure 3 shows the interconnections for bipolar op-

eration. Connect I

O1, IO2, FB1, FB3, FB4 as shown in

diagram. Tie LDTR to I

O2. As shown, a series resistor

isrecommendedintheV

DDsupplylinetolimitcurrent

during‘turn-on.Tomaintainspecifiedlinearity,exter-

nal amplifiers must be zeroed. This is best done with

REF set to zero and, the DAC register loaded with

10...0 (MSB = 1). Set R

0S1 for V01 = 0. Set R0S2 for

OUT = 0. Set VREF to +10V and adjust RB for VOUT

to be 0V.

Grounding

Connect all GND pins to system analog ground

and tie this to digital ground. All unused input pins

must be grounded.

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