HS7541A

12-Bit CMOS Multiplying DAC

© Copyright 2000 Sipex Corporation

6

minal, may be anywhere between 10k

Ω (the

feedback resistor alone when all digital inputs

are LOW) and 7.5k

Ω (the feedback resistor in

parallel with approximately 30k

Ω of the R-2R

ladder network resistance when any single bit is

HIGH). Static accuracy and dynamic perfor-

mance will be affected by these variations.

UNIPOLAR OPERATION

Figure 4 shows the connections to implement

digital unipolar operation of the HS7541A. The

reference voltage applied to V

positive or negative. The 2K

Ω potentiometer

tied to V

back loop are both optional; they are needed

only when gain error must be trimmed to less

than 0.3% FSR. They should track each other to

better than 0.1%. It is not necessary that they

track the resistors internal to the HS7541A.

Figure 5. Bipolar Operation

INPUT

DATA

2K

Ω

GAIN TRIM

1K

Ω

–

+

GND

+15V

4

15

3

2

1

18

16

17

HS7541A

–

+

10K

Ω

10K

Ω

10K

Ω

390

Ω

500

Ω

As shown in the figure, the output current of the

HS7541A is typically connected to an external

op amp, with its non-inverting input tied to

ground. The amplifier should be selected for

low input bias current and low drift over tem-

perature. To maintain the specified linearity, the

amplifier’s input offset voltage should be mulled

to less than

±200µV (0.1 LSB).

BIPOLAR OPERATION

Figure 5 shows the connections for bipolar

operation of the HS7541A. The digital input

coding is offset binary as shown in Table 2. As

is the case for unipolar operation, the gain trim

resistors can be omitted if minimum gain error

is not required. The op amp selection criteria

and offset nulling are the same as for unipolar

operation.

DIGITAL INPUT

I

0UT

1111 1111 1111

-0.99975 x V

REF

1000 0000 0000

-0.50000 x V

REF

0111 1111 1111

-0.49975 x V

REF

0000 0000 0000

0V

Table 1. Unipolar Input Coding

DIGITAL INPUT

I

0UT

1111 1111 1111

-0.99951 x V

REF

1000 0000 0001

-0.00049 x V

REF

1000 0000 0000

0V

0100 0000 0000

+0.50000 x V

REF

0000 0000 0000

+1.00000 x V

REF

Table 2. Bipolar Input Coding