SP3238E datasheet(10/20 Pages) SIPEX

10 / 20 page

SP3238EDS/04

SP3238E +3.0V to +5.5V RS-232 Transceivers

Since receiver input is usually from a transmission

line where long cable lengths and system

interference can degrade the signal, the inputs

have a typical hysteresis margin of 300mV. This

ensures that the receiver is virtually immune to

noisy transmission lines. Should an input be left

unconnected, an internal 5k

Ω pulldown resistor

to ground will commit the output of the receiver

to a HIGH state.

Charge Pump

The charge pump is a Sipex–patented design

(U.S. 5,306,954) and uses a unique approach

compared to older less–efficient designs. The

charge pump still requires four external

capacitors, but uses a four–phase voltage

shifting technique to attain symmetrical 5.5V

power supplies.

The internal power supply

consists of a regulated dual charge pump that

provides output voltages 5.5V regardless of the

input voltage (V

CC) over the +3.0V to +5.5V

range. This is important to maintain compliant

RS-232 levels regardless of power supply

fluctuations.

The charge pump operates in a discontinuous

mode using an internal oscillator. If the output

voltages are less than a magnitude of 5.5V, the

charge pump is enabled. If the output voltages

exceed a magnitude of 5.5V, the charge pump is

disabled. This oscillator controls the four phases

of the voltage shifting. A description of each

phase follows.

Phase 1

— V

SS charge storage — During this phase of

the clock cycle, the positive side of capacitors

1 and C2 are initially charged to VCC.

+ is

then switched to GND and the charge in C

– is

transferred to C

–. Since C

+ is connected to

CC, the voltage potential across capacitor C2 is

now 2 times V

CC.

Phase 2

— V

SS transfer — Phase two of the clock

connects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

to GND. This transfers a negative generated

voltage to C

3. This generated voltage is

regulated to a minimum voltage of -5.5V.

Simultaneous with the transfer of the voltage to

3, the positive side of capacitor C1 is switched

to V

CC and the negative side is connected to

GND.

Phase 3

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –VCC in the negative

terminal of C

1, which is applied to the negative

side of capacitor C

Since C

+ is at V

CC, the

voltage potential across C

2 is 2 times VCC.

Phase 4

— V

DD transfer — The fourth phase of the clock

connects the negative terminal of C

2 to GND,

and transfers this positive generated voltage

across C

2 to C4, the VDD storage capacitor. This

voltage is regulated to +5.5V. At this voltage,

the internal oscillator is disabled. Simultaneous

with the transfer of the voltage to C

4, the

positive side of capacitor C

1 is switched to VCC

and the negative side is connected to GND,

allowing the charge pump cycle to begin again.

The charge pump cycle will continue as long as

the operational conditions for the internal

oscillator are present.

Since both V+ and V– are separately generated

from V

CC, in a no–load condition V

+ and V– will

be symmetrical. Older charge pump approaches

that generate V– from V+ will show a decrease in

the magnitude of V– compared to V+ due to the

inherent inefficiencies in the design.

The clock rate for the charge pump typically

operates at 500kHz. The external capacitors can

be as low as 0.1

µF with a 16V breakdown

voltage rating.

SP3238E 데이터시트(PDF) 10 Page - Sipex Corporation

SP3238E 데이터시트(HTML) 10 Page - Sipex Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

데이터시트 다운로드

링크 URL