5

SP3483 DS/04

SP3483 Low Power Slew Rate Limited Half-Duplex RS485 Transceivers

© Copyright 2000 Sipex Corporation

INPUTS

OUTPUTS

LINE

RE

DE

DI CONDITION

B

A

X

1

1

No Fault

0

1

X

1

0

No Fault

1

0

X0

X

X

ZZ

INPUTS

OUTPUTS

RE

DE

A - B

R

0

0

+0.2V

1

0

0

-0.2V

0

0

0

Inputs Open

1

10

X

Z

Table 1. Transmit Function Truth Table

Table 2. Receive Function Truth Table

Figure 2. Driver Propagation Delay Test Circuit

Figure 4. Driver Enable and Disable Timing Circuit,

Output HIGH

Figure 1. Driver DC Test Load Circuit

Figure 6. Receiver Propagation Delay Test Circuit

Figure 7. Receiver Enable and Disable Timing Circuit

R

R

D

GENERATOR

(NOTE 1)

50

Ω

S1

Ω

OUT

(NOTE 2)

1.5V

2

D

GENERATOR

(NOTE 1)

50

Ω

S1

Ω

OUT

(NOTE 2)

1.5V

2

D

GENERATOR

(NOTE 1)

50

Ω

S1

Ω

OUT

(NOTE 2)

D

0V OR 3V

GENERATOR

(NOTE 1)

50

Ω

1.5V

0V

R

OUT

(NOTE 2)

2

1.5V

-1.5V

S3

GENERATOR

(NOTE 1)

50

Ω

(NOTE 2)

R

1k

S1

S2

Figure 5. Driver Enable and Disable Timing Circuit,

Output LOW

GENERATOR

(NOTE 1)

50

Ω

OUT

D

60

Ω

Figure 3. Driver Differential Output Delay and Transition

Time Circuit