SP526 datasheet(17/23 Pages) SIPEX

17 / 23 page

Rev: B Date:7/7/04

SP526 Multi–Mode Serial Transceiver

The third type of receiver is a differential which

supports RS-422/V.11 signals. This receiver

has a typical input impedance of 10K

Ω and a

differential threshold of

±0.3V, which complies

with the RS-422/V.11 specifications. Since the

characteristics of the RS-422 (V.11) receivers

are actually subsets of RS-485, the RS-422/

V.11 receivers can accept RS-485 signals.

However, these receivers cannot support 32

transceivers on the signal bus due to the lower

input impedance as specified in the RS-485

specifications.

V.11 receivers are used in

RS-422, RS-449, EIA-530, EIA-530A and V.36

as Category I signals for receiving clock, data,

and some control line signals not covered

by Category II V.10 circuits. The differential

receivers can receive signals up to at least

10Mbps.

All four receivers include an enable line for

tri-state of the receiver output allowing

convenient half-duplex configurations. When

the enable lines are at a logic LOW ("0") active,

the receiver outputs are high impedance and will

be at approximately 10k

Ω during tri-state.

All receivers include a fail-safe feature that

outputs a logic high when the receiver inputs are

open. For single-ended RS-232 receivers, there

are internal 5k

Ω pull-down resistors on the

inputs which produces a logic high ("1") at the

receiver outputs. The single-ended RS-423

receivers produce a logic LOW ("0") on the

output when the inputs are open. This is due to

a pull-up device connected to the input. The

differential receivers have the same internal

pull-up device on the non-inverting input which

produces a logic HIGH ("1") at the receiver output.

Charge Pump

The charge pump is a Sipex–patented design

(U.S. 5,306,954) and uses a unique approach

compared to older less–efficient designs. The

charge pump still requires four external capaci-

tors, but uses a four–phase voltage shifting

technique to attain symmetrical 10V power

supplies. There is a free–running oscillator that

controls the four phases of the voltage shifting.

A description of each phase follows.

Phase 1

— V

SS charge storage —During this phase of

the clock cycle, the positive side of capacitors

1 and C2 are initially charged to +5V. Cl

+ is

then switched to ground and the charge in C

– is

transferred to C

–. Since C

+ is connected to

+5V, the voltage potential across capacitor C

2 is

now 10V.

Phase 2

— V

SS transfer — Phase two of the clock

connects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

to ground, and transfers the generated –l0V to

3. Simultaneously, the positive side of

capacitor C

1 is switched to +5V and the

negative side is connected to ground.

Phase 3

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –5V in the negative

terminal of C

1, which is applied to the negative

side of capacitor C

2. Since C2

+ is at +5V, the

voltage potential across C

2 is l0V.

-5V

VCC = +5V

+5V

-5V

VDD Storage Capacitor

VSS Storage Capacitor

Figure 30. Charge Pump — Phase 1

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