13

Date: 5/25/04

© Copyright 2004 Sipex Corporation

switch. It is during this interval that the 3%

window comparator has taken control away from

the main loop. The main loop regains control

only if the output voltage crosses through its

regulated value.

Also notice where the 3%

comparator takes over. The output voltage is

considered “high” only if the trough of the ripple

is above 3%. The output voltage is considered

“low” only if the peak of the ripple is below 3%.

By managing the secondary loop in this fashion,

the SP6120 can improve the transient response

of high performance power converters without

causing strange disturbances in low to moderate

performance systems.

Driver Logic

Signals from the PWM latch (QPWM), Fault

latch (FAULT), Program Logic, Zero Crossing

Comparator, and 3% Window Comparators all

flow into the Driver Logic. The following is a

truth table for determining the state of the GH

and GL voltages for given inputs:

E

L

B

A

T

H

T

U

R

T

C

I

G

O

L

R

E

V

I

R

D

T

L

U

A

F1

100000000

r

o

M

W

P

Q

P

M

O

C

%

3

XX

11

000000

T

E

F

P

/

T

E

F

NN

P

N

P

N

PN

PN

P

C

S

I

D

/

T

N

O

CX

XX

XC

C

DDDD

S

S

O

R

C

O

R

E

ZX

X

XXXX

0

0

1

1

H

G0

1

1

0

0

10

10

1

L

G0

00

0

1111

00

The QPWM and 3% Comparators are grouped

together because 3% Low is the same as QPWM

= 1 and 3% High is the same as QPWM = 0.

Output Drivers

The driver stage consists of one high side, 4

Ω

driver, GH and one low side, 4

Ω, NFET driver,

GL. As previously stated, the high side driver

can be configured to drive a PFET or an NFET

high side switch. The high side driver can also be

configured as a switch node referenced driver.

Due to voltage constraints, this mode is manda-

tory for 5V, single supply, high side NFET

applications. The following figure shows typical

driver waveforms for the 5V, high side NFET

design.

As with all synchronous designs, care must be

taken to ensure that the MOSFETs are properly

chosen for non-overlap time, peak current capa-

bility and efficiency.

GATE DRIVER TEST CONDITONS

5V

90%

10%

GH (GL)

2V

5V

GH (GL)

2V

NON-OVERLAP

RISE TIME

FALL TIME

90%

10%

V(BST)

0V

GH

Voltage

0V

GL

Voltage

SWN

Voltage

~0V

~V(Diode) V

BST

Voltage

TIME

THEORY OF OPERATIONS: Continued