DS1821 datasheet(13/19 Pages) MAXIM

13 / 19 page

DS1821

13 of 19

Figure 9 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15 µs for a read time slot.

Figure 10 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible

and by locating the master sample time during read time slots towards the end of the 15 µs period.

READ/WRITE TIME SLOT TIMING DIAGRAM Figure 8

DETAILED MASTER READ 1 TIMING Figure 9

RECOMMENDED MASTER READ 1 TIMING Figure 10

VDD

GND

1-WIRE BUS

15 µs

VIH of Master

TRC

TINT > 1 µs

Master samples

VDD

GND

1-WIRE BUS

15 µs

VIH of Master

TRC =

small

TINT =

small

Master samples

LINE TYPE LEGEND (Figure 8, Figure 9 and Figure 10)

Bus master pulling low

DS1821 pulling low

Resistor pullup

45 µs

15 µs

VDD

GND

1-WIRE BUS

60 µs < TX “0” < 120

1 µs < TREC < ∞

DS1821 samples

MIN

TYP

MAX

15 µs

30 µs

> 1 µs

MASTER WRITE “0” SLOT

MASTER WRITE “1” SLOT

DS1821 samples

MIN

TYP

MAX

VDD

GND

1-WIRE BUS

15 µs

MASTER READ “0” SLOT

MASTER READ “1” SLOT

Master samples

START

OF SLOT

START

OF SLOT

> 1 µs

1 µs < TREC < ∞

15 µs

30 µs

15 µs

> 1 µs

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