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SL4029BN 데이터시트(PDF) 5 Page - System Logic Semiconductor

부품명 SL4029BN
상세설명  Presettable Up/Down Counter
PDF  8 Pages
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제조업체  SLS [System Logic Semiconductor]
홈페이지  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL4029BN 데이터시트(HTML) 5 Page - System Logic Semiconductor

  SL4029BN Datasheet HTML 1Page - System Logic Semiconductor SL4029BN Datasheet HTML 2Page - System Logic Semiconductor SL4029BN Datasheet HTML 3Page - System Logic Semiconductor SL4029BN Datasheet HTML 4Page - System Logic Semiconductor SL4029BN Datasheet HTML 5Page - System Logic Semiconductor SL4029BN Datasheet HTML 6Page - System Logic Semiconductor SL4029BN Datasheet HTML 7Page - System Logic Semiconductor SL4029BN Datasheet HTML 8Page - System Logic Semiconductor  
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SL4029B
System Logic
Semiconductor
SLS
TIMING REQUIREMENTS(C
L=50pF, RL=200 k
Ω, Input t
r=tf=20 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
≥-55°C
25
°C
≤125°C
Unit
tw
Minimum Pulse Width, Clock (Figure 1)
5.0
10
15
180
90
60
180
90
60
360
180
120
ns
tw
Minimum Pulse Width, Preset Enable
(Figure 1)
5.0
10
15
130
70
50
130
70
50
260
140
100
ns
tsu
*
Minimum Setup Time, Clock to B/D or U/D
(Figure 1)
5.0
10
15
340
140
100
340
140
100
680
280
200
ns
trem
*
Minimum Removal Time, Preset Enable (Figure 1)
5.0
10
15
200
110
80
200
110
80
400
220
160
ns
th
**
Minimum Hold Time, Clock to Carry In (Figure 2)
5.0
10
15
50
30
25
50
30
25
100
60
50
ns
tsu
MinimumSetup Time, Carry In to Clock (Figure
1)
5.0
10
15
200
70
60
200
70
60
400
140
120
ns
tr, tf
**
Maximum Input Rise and Fall Times,Clock
(Figure 2)
5.0
10
15
15
15
15
15
15
15
30
30
30
µs
* From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge.
** From Carry In to Clock Edge



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