SL74HC165

System Logic

Semiconductor

SLS

8-Bit Serial or Parallel-Input/

Serial-Output Shift Register

High-Performance Silicon-Gate CMOS

The SL74HC165 is identical in pinout to the LS/ALS165. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

This device is an 8-bit shift register with complementary outputs

from the last stage. Data may be loaded into the register either in

parallel or in serial form. When the Serial Shift/ Parallel Load input is

low, the data is loaded asynchronously in parallel. When the Serial

Shift/Parallel Load input is high, the data is loaded serially on the rising

edge of either Clock or Clock Inhibit (see the Function Table).

The 2-input NOR clock may be used either by combining two

independent clock sources or by designating one of the clock inputs to

act as a clock inhibit.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC165N Plastic

SL74HC165D SOIC

° to 125° C for all packages

LOGIC DIAGRAM

PIN 8 = GND

FUNCTION TABLE

Inputs

Internal Stages

Output

Operation

Serial Shift/

Parallel Load

Clock

Clock

Inhibit

A-H

L

H

X

X

a...h

a

b-g

h

Asynchronous Parallel Load

H

L

L

X

L

Serial Shift via Clock

H

L

H

X

H

H

L

L

X

L

Serial Shift via Clock

H

L

H

X

H

Inhibit

H

X

H

X

X

no change

Inhibited Clock

H

H

X

X

X

H

L

L

X

X

no change

No Clock

X = Don’t Care

PIN ASSIGNMENT