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SL74HC175 데이터시트(PDF) 1 Page - System Logic Semiconductor |
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SL74HC175 데이터시트(HTML) 1 Page - System Logic Semiconductor |
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1 / 5 page ![]() SL74HC175 System Logic Semiconductor SLS Quad D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The SL74HC175 is identical in pinout to the LS/ALS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of four D flip-flops with common Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive-going edge of the Clock input. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC175N Plastic SL74HC175D SOIC TA = -55 ° to 125° C for all packages PIN ASSIGNMENT FUNCTION TABLE Inputs Outputs Reset Clock D Q Q L X X L H H H H L H L L H H L X no change X = Don’t care LOGIC DIAGRAM PIN 16=VCC PIN 8 = GND |
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