AD9518-2ABCPZ datasheet(37/64 Pages) AD

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Data Sheet

AD9518-2

Rev. C | Page 37 of 64

Synchronizing the Outputs—Sync Function

The AD9518 clock outputs can be synchronized to each other.

Outputs can be individually excluded from synchronization.

Synchronization consists of setting the nonexcluded outputs to

a preset set of static conditions and subsequently releasing these

outputs to continue clocking at the same instant with the preset

conditions applied. This allows for the alignment of the edges of

two or more outputs or for the spacing of edges according to the

coarse phase offset settings for two or more outputs.

Output synchronization is executed in several ways, as follows:



By forcing the SYNC pin low, then releasing it (manual sync).



By setting, then resetting, any one of the following three bits:

the soft sync bit (Register 0x230[0]), the soft reset bit

(Register 0x000[2] [mirrored]), and the power-down

distribution reference bit (Register 0x230[1]).



By executing synchronization of the outputs as part of the

chip power-up sequence.



By forcing the RESET pin low, then releasing it (chip reset).



By forcing the PD pin low, then releasing (chip power-down).



Following completion of a VCO calibration. An internal

SYNC signal is automatically asserted at the beginning of

a VCO calibration, then released upon its completion.

The most common way to execute the sync function is to use

the SYNC pin to do a manual synchronization of the outputs.

This requires a low-going signal on the SYNC pin, which is held

low and then released when synchronization is desired. The

timing of the sync operation is shown in Figure 41 (using the

VCO divider) and Figure 42 (VCO divider not used). There is

an uncertainty of up to one cycle of the clock at the input to the

channel divider due to the asynchronous nature of the SYNC

signal with respect to the clock edges inside the AD9518. The

delay from the SYNC rising edge to the beginning of synchronized

output clocking is between 14 and 15 cycles of clock at the

channel divider input, plus either one cycle of the VCO divider

input (see Figure 41), or one cycle of the channel divider input (see

Figure 42), depending on whether the VCO divider is used.

Cycles are counted from the rising edge of the signal.

Another common way to execute the sync function is by setting

and resetting the soft sync bit at Register 0x230[0] (see Table 43

through Table 49 for details). Both the setting and resetting

of the soft sync bit require an update all registers operation

(Register 0x232[0] = 1) to take effect.

910

INPUT TO VCO DIVIDER

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 41. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input

INPUT TO CLK

IINPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

910

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 42. SYNC Timing When VCO Divider Is Not Used—CLK Input Only

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