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SL74HC299 데이터시트(PDF) 5 Page - System Logic Semiconductor |
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SL74HC299 데이터시트(HTML) 5 Page - System Logic Semiconductor |
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5 / 8 page ![]() SL74HC299 System Logic Semiconductor SLS TIMING REQUIREMENTS(C L=50pF,Input t r=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to-55°C ≤85°C ≤125°C Unit tsu Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tsu Minimum Setup Time, Data Inputs SA, SH, PA thru PH to Clock (Figure 4) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns th Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) 2.0 4.5 6.0 120 24 20 150 30 26 180 36 31 ns th Minimum Hold Time, Clock to Data Inputs, SA, SH, PA thru PH (Figure 4) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns |
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