SL74HC4015

System Logic

Semiconductor

SLS

Dual 4-Bit Shift Register

High-Performance Silicon-Gate CMOS

The device inputs are compatible with standard CMOS outputs;

with pullup resistors, they are compatible with LS/ALSTTL outputs.

This device consists of two identical independent 4-stage serial-

input/parallel-output registers. Each register has independent Clock

and Reset inputs as well as a single serial Data input. “Q” outputs are

available from each of the four stages on both registers. All register

stages are D-type, master-slave flip-flops. The logic level present at the

Data input is transferred into the first register stage and shifted over

one stage at each positive-going clock transition. Resetting of all

stages is accomplished by a high level on the reset line.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC4015N Plastic

SL74HC4015D SOIC

° to 125° C for all packages

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Outputs

Clock

Data

Reset

L

L

L

H

L

H

X

L

*

*

X

X

H

L

L

X = don’t care

LOGIC DIAGRAM

PIN 8 = GND